The present invention relates to ROMs (read-only memories), and in particular to a method of reading data from multiple bit line ROMs.
1. Field of the Invention
There is a general motivation in the field of ROM cell technology to produce smaller ROM cells than are currently available, so that chip areas can be reduced while still storing large amounts of data.
2. Description of the Related Art
ROMs are typically based on arrays of transistors. For example, NMOS transistors may be used. One configuration using NMOS transistors involves an array in which each transistor is grounded at its source terminal 10 as shown in FIG. 1. Alternatively, PMOS transistors may be used, or a combination of both NMOS and PMOS. In any case, the transistors will typically be arranged in columns 11 and rows 12 as can be seen in FIG. 1. Transistors in the same row 12 will share a common gate connection 13, referred to herein as a word line. Transistors in the same column 11 will share a single output wire 14, referred to herein as a bit line.
Programming of the NMOS ROM shown in FIG. 1, is achieved by selectively connecting the bit lines 14 to the drain terminals 15 of the transistors in the array. A connection may be made by inserting a via 16 between a bit line and a drain. In an NMOS ROM, a via 16 programmes a “0” bit. Conversely, a non-connection 17 programmes a “1” bit.
A ROM is read using the gate 18 and the drain 15 terminals of the transistors. First, all word lines 13 are grounded and the bit lines are pre-charged to VDD. Next, the pre-charging circuitry is switched off and the appropriate word line 13 is activated, that is, a positive voltage VCC is applied to the word line. If there is a connection 16 between an activated transistor and a bit line, the voltage on the bit line will be pulled down to zero volts, and can be interpreted as a “0” in the data. If there is no connection 17 between an activated transistor and a bit line, the bit line will remain floating and will give a high voltage (a “1”).
It can clearly be seen that the technique described above only allows for one bit of data to be stored per transistor. Since the density at which interconnects can be defined is much greater than the density at which transistors can be defined, it is desirable to create a ROM structure in which multiple bits may be stored per transistor. In such a structure, the bits may be encoded by means of multiple available configurations of interconnects to the transistor.
One way of implementing the concept of storing multiple bits per transistor is to have multiple bit lines 24 for each column 21, as shown in FIG. 2A. However, it should be noted that the number of bits that can be stored in each ROM cell is not proportional to the number of bit lines (X, Y, Z) per column. This is because connections to more than one bit line for a given transistor will short the different bit lines together and will not give a meaningful reading. This situation is shown as 22 in FIG. 2A.
Since multiple bit line connections per transistor are not possible, there are four possible states that can be used to store data in the ROM cell depicted in FIG. 2A. 26, 27 and 28 show vias connected between drain terminals and bit lines X, Y and Z respectively. 25 shows a fourth possible state in which the drain terminal is not connected to any of bit lines X, Y or Z.
The four states can be detected in a manner similar to that used for a standard single bit line ROM cell, as described above. The states can be decoded into a series of 2-bit words, as shown in the following truth table:
TABLE 1Configuration(see FIG. 2)XYZBit 1Bit 22511100260110127101102811011
Table 1 is merely one example of one way in which the detected values may be decoded. In the present example of an NMOS ROM cell, a reading of “111” would mean that no connections were in place between the drain terminal of the transistor and the bit lines X, Y and Z. In the example of Table 1, the state 111 would mean a word “00” had been encoded. A reading of “101” would mean that a via was in place between terminal Y and the drain terminal, and this would correspond to the word “10”.
In general, 2n n-bits words can be encoded into 2n−1 bit line connections. However, it has been found that in practice it is only useful to use three bit lines (n=2).
U.S. Pat. Nos. 6,355,550 and 6,498,066 disclose ROMs using three bit lines per column. The ROMs are embedded in multi-layered integrated circuits. FIG. 2B shows a representation of the possible connections in such prior art ROMs. “x” represents a position where a via may be placed in order to form a connection. Connections may be made at points 200, 201 or 202 between conductive pad 220 and bit lines 210, thus giving four possible states (200, 201, 202 or no connection).
ROM cells such as those described above are typically fabricated using a series of masks and applying a series of patterned layers to a substrate. (See U.S. Pat. Nos. 6,355,550 and 6,498,066.)
One of the potential problems concerning multiple bit line ROMs is the effect of capacitive coupling. Distortion of stored data can arise if a change in voltage on one bit line causes a corresponding change in an adjacent bit line through capacitive charge sharing. FIG. 3 illustrates the process of this capacitive charge sharing.
In the pre-charge state, two adjacent bit lines are connected to voltage VDD. In this state, V(bit line 1)=V(bit line 2)=VDD.
In the discharge state the bit lines are disconnected from VDD and instead bit line 1 is grounded and bit line 2 is left floating. In this state, V(bit line 1)=0 and V(bit line 2)=VDD×CB2/(CB2+CC), where CC is the capacitance between bit lines 1 and 2 through the dielectric substrate that separates them. Thus, some of the charge stored in CB2 moves onto CC and the voltage on bit line 2 is reduced. If CC is large enough compared to CB2, the voltage on bit line 2 may incorrectly be read as a “0”.
In single bit line ROMs, this problem can be overcome by interleaving columns of bit cells and grounding bit lines associated with unused bit cells. For example, odd columns could be used for odd addresses and even columns for even addresses. In this way, at any given time the bit lines adjacent to a sensitive bit line will be grounded, and no coupling can occur.
However, with multi-bit ROMs the situation is more complicated since the three bit lines associated with each column will all be sensitive at the same time. The problem of coupling therefore remains to be solved in a different way.
A further disadvantage that may be found with known multiple bit line ROMs is that several masks may need to be remade when a ROM is to be reprogrammed. A particular set of masks will be appropriate for a particular set of data to be programmed into a ROM, but when a different set of data need to be programmed several masks may need to be altered to produce different patterns on the substrate.
It is therefore an aim of the present invention to produce a multiple bit memory cell, and a method of reading such a memory cell, that can overcome the above-stated problems and disadvantages.